Publications by the
Duke Computer Architecture Group
Refer to the ACM
and/or IEEE copyright policy for ACM publications, here
"Fractal Coherence: Scalably Verifiable Cache Coherence." Meng Zhang, Alvin R. Lebeck, and Daniel J. Sorin. To appear in 43rd International Symposium on Microarchitecture (MICRO), December 2010.
"Specifying and Dynamically Verifying Address Translation-Aware Memory Consistency." Bogdan F. Romanescu, Alvin R. Lebeck, and Daniel J. Sorin. 15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2010), March 2010.
Routing in Self-Organizing Nano-Scale Irregular Networks, Y. Liu, C. Dwyer, A. R. Lebeck, To appear in ACM Journal on Emerging Technologies in Computing (JETC) 2010
Architectural Implications of Nanoscale Integrated Sensing and Computing, C. Pistol, W. Chongchitmate, C. Dwyer, A. R. Lebeck, To appear in IEEE MICRO Top Picks in Computer Architecture, 2010.
UNified Instruction/Translation/Data (UNITD) Coherence: One Protocol to Rule Them All. Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin, and Anne Bracy. 16th IEEE International Symposium on High-Performance Computer Architecture, January 2010.
Reduced Precision Checking for a Floating Point Adder. Patrick J. Eibl, Daniel J. Sorin, and Andrew D. Cook. 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, October 2009.
Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms. Meng Zhang, Anita Lungu, and Daniel J. Sorin. 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, October 2009.
Dynamic Power Gating with Quality Guarantees. Anita Lungu, Pradip Bose, Alper Buyuktosunoglu and Daniel J. Sorin. International Symposium on Low Power Electronics and Design (ISLPED), August 2009.
Multicore Power Management: Ensuring Robustness via Early-Stage Formal Verification. Anita Lungu, Pradip Bose, Daniel Sorin, Steven German and Geert Janssen. Seventh ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE), July 2009.
Architectural Implications of Nanoscale Integrated Sensing and Computing, C. Pistol, W. Chongchimate, C. Dwyer, A. R. Lebeck, Proceedings of the Fourteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '09), March 2009. (to appear)
Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures, Albert Meixner and Daniel J. Sorin. IEEE Transactions on Dependable and Secure Computing (TDSC), volume 6, number 1, January-March 2009.
Nanoscale Optical Computing using Resonance Energy Transfer Logic, C. Pistol, C. Dwyer, A. R. Lebeck, IEEE MICRO November/December, 2008 (to appear).
Multicore Power Management: Ensuring Robustness via Early-Stage Formal Verification, Anita Lungu, Pradip Bose, Daniel J. Sorin, Steven German, and Geert Janssen, 3rd Workshop on Dependable Architectures (WDA-3), November 2008.
Self-Assembled Computer Architecture, C. Dwyer and A. R. Lebeck, (Invited chapter), Systems Self-Assembly: multidisciplinary snapshots, eds. N. Krasnogor, et al. Elsevier, 2008
An Introduction to DNA Self-assembled Computer Design, C. Dwyer, A. R. Lebeck, Artech House Publishers, 2008.
Core Cannibalization Architecture: Improving Lifetime Chip Performance for Multicore Processors in the Presence of Hard Faults, Bogdan F. Romanescu and Daniel J. Sorin. Seventeenth International Conference on Parallel Architectures and Compilation Techniques (PACT), October 2008.
Detouring: Translating Software to Circumvent Hard Faults in Simple Cores, Albert Meixner and Daniel J. Sorin. 38th Annual International Conference on Dependable Systems and Networks (DSN), June 2008.
IOTA: Detecting Erroneous I/O Behavior via I/O Transaction Auditing, Albert Meixner and Daniel J. Sorin. First Workshop on Compiler and Architectural Techniques for Application Reliability and Security (CATARS), June 2008.
The Impact of Dynamically Heterogeneous Multicore Processors on Thread Scheduling, Fred A. Bower, Daniel J. Sorin, and Landon P. Cox. IEEE Micro, May/June 2008.
Reducing the Impact of Intra-Core Process Variability with Criticality-Based Resource Allocation and Prefetching, Bogdan F. Romanescu, Michael E. Bauer, Daniel J. Sorin, and Sule Ozev. ACM International Conference on Computing Frontiers, May 2008.
Argus: Low-Cost, Comprehensive Error Detection in Simple Cores, Albert Meixner, Michael E. Bauer, and Daniel J. Sorin. IEEE Micro: Micro's Top Picks from Computer Architecture Conferences, January/February 2008.
Argus: Low-Cost, Comprehensive Error Detection in Simple Cores, Albert Meixner, Michael E. Bauer, and Daniel J. Sorin. 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), December 2007.
Low-Cost Run-time Diagnosis of Hard Delay Faults in the Functional Units of a Microprocessor, Sule Ozev, Daniel J. Sorin, and Mahmut Yilmaz. IEEE International Conference on Computer Design (ICCD), October 2007.
Lazy Error Detection for Microprocessor Functional Units, Mahmut Yilmaz, Albert Meixner, Sule Ozev, and Daniel J. Sorin. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS), September 2007.
Verification-Aware Microprocessor Design, Anita Lungu and Daniel J. Sorin. Sixteenth International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2007.
Error Detection Using Dynamic Dataflow Verification, Albert Meixner and Daniel J. Sorin. Sixteenth International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2007.
Reducing the Impact of Process Variability with Prefetching and Criticality-Based Resource Allocation, Bogdan F. Romanescu, Michael E. Bauer, Daniel J. Sorin, and Sule Ozev. Poster and extended abstract in Sixteenth International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2007.
Self-Organizing Defect Tolerant, Self-Assembled Nanoscale Architectures, A. R. Lebeck, C. Dwyer, in Nanoelectronic Devices for Defense and Security Conference, June 2007.
Energy Transfer Logic on DNA Nanostructures: Enabling Molecular-Scale Amorphous Computing, C. Dwyer, A. R. Lebeck, C. Pistol, in Proceedings of the 4th Workshop on Non-Silicon Computing, pages 33-40, June 2007
A Defect Tolerant Self-organizing Nanoscale SIMD Architecture, J. Patwardhan, V. Johri, C. Dwyer, A. R. Lebeck, in ACM Journal on Emerging Technologies in Computing (JETC), Volume 3, No. 2, July 2007.
Online Diagnosis of Hard Faults in Microprocessors, Fred A. Bower, Daniel J. Sorin, and Sule Ozev, ACM Transactions on Architecture and Code Optimization (TACO), volume 4, number 2, June 2007.
Scalable, Low-cost, Hierarchical Assembly of Programmable DNA Nanostructures, C. Pistol and C. Dwyer., Nanotechnology, vol. 18, 125305-9, 2007.
Unified Microprocessor Core Storage, Albert Meixner and Daniel J. Sorin, ACM Conference on Computing Frontiers, May 2007.
Error Detection via Online Checking of Cache Coherence with Token Coherence Signatures, Albert Meixner and Daniel J. Sorin, 13th International Symposium on High-Performance Computer Architecture (HPCA), February 2007.
Quantifying the Impact of Process Variability on Microprocessor Behavior, Bogdan F. Romanescu, Sule Ozev, and Daniel J. Sorin, 2nd Workshop on Architectural Reliability (WAR), December 2006.
A Defect Tolerant Self-organizing Nanoscale SIMD Architecture, J. Patwardhan, V. Johri, C. Dwyer, A. R. Lebeck, in Proceedings of the Twelth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS XII), October 2006.
Self-Detecting and Self-Diagnosing 32-bit Microprocessor Multiplier, M. Yilmaz, D.R. Hower, S. Ozev, and D.J. Sorin, International Test Conference (ITC), October 2006.
Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache, N.N. Sadler and D.J. Sorin, International Conference on Computer Design (ICCD), October 2006.
Self-Assembled Networks: Control vs. Complexity, Jaidev Patwardhan, Chris Dwyer, Alvin R. Lebeck. 1st International Conference on Nano-Networks (NANONETS), September 2006.
Design and Evaluation of Fail-Stop Self-Assembled Nanoscale Processing Elements, J. Patwardhan, C. Dwyer, A. R. Lebeck, in IEEE International Workshop on Design and Test of Defect-Tolerant Nanoscale Architectures (NANOARCH '06), June 2006
Design Automation for DNA Self-Assembled Nanostructures, C. Pistol, C. Dwyer, A. R. Lebeck, in Proceedings of the 43rd Design Automation Conference (DAC), July, 2006.
NANA: A Nano-scale Active Network Architecture, J. Patwardhan, C. Dwyer, A. R. Lebeck, D. J. Sorin, ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 2, No. 1, Pages 1-30, January 2006.
Spin Detection Hardware for Improved Management of Multithreaded System. T. Li, A. R. Lebeck, D. J. Sorin, IEEE Transactions on Parallel and Distributed Systems, volume 17, number 6, June 2006.
Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures. Albert Meixner and Daniel J. Sorin. International Conference on Dependable Systems and Networks (DSN), June 2006.
Applying Architectural Vulnerability Analysis to Hard Faults in the Microprocessor. Fred A. Bower, Derek H. Hower, Mahmut Yilmaz, Daniel J. Sorin, and Sule Ozev. Poster and 2-page paper in ACM SIGMETRICS, June 2006.
Finite-size, Fully-Addressable DNA Tile Lattices Formed by Hierarchical Assembly Procedures, S. H. Park, C. Pistol, S. J. Ahn, J. H. Reif, A. R. Lebeck, C. Dwyer, T. H. LaBean, Volume 45, Issue 5, Pages: 735-739, January 23, 2006.
Self-Assembled Computer Architecture, C. Dwyer and A. R. Lebeck, (Invited chapter) to appear, Systems Self-Assembly: multidisciplinary snapshots, eds. N. Krasnogor, et al.
Autonomic Microprocessor Execution via Self-Repairing Arrays. Fred A. Bower, Sule Ozev, and Daniel J. Sorin. IEEE Transactions on Dependable and Secure Computing, October-December 2005.
A Mechanism for Online Diagnosis of Hard Faults in Microprocessors, Fred A. Bower, Daniel J. Sorin, and Sule Ozev. 38th Annual International Symposium on Microarchitecture (MICRO), November 2005.
Multifacet's General Execution-driven Multiprocessor Simulator (GEMS) Toolset, Milo M.K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, and David A. Wood. Computer Architecture News (CAN), September 2005.
Dynamic Verification of Sequential Consistency, Albert Meixner and Daniel J. Sorin. 32nd Annual International Symposium on Computer Architecture (ISCA), June 2005.
Evaluating the Connectivity of Self-Assembled Networks of Nano-scale Processing Elements, Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck, Daniel J. Sorin, IEEE International Workshop on Design and Test of Defect-Tolerant Nanoscale Architectures (NANOARCH’05), May 2005.
Pulse: A Dynamic Deadlock Detection Mechanism Using Speculative Execution, Tong Li, Carla S. Ellis, Alvin R. Lebeck, and Daniel J. Sorin. USENIX Annual Technical Conference, April 2005.
Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown, Jonathan R. Carter, Sule Ozev, and Daniel J. Sorin, Design, Automation, and Test in Europe (DATE), March 2005.
Experiences in Managing Energy with ECOSystem, H. Zengh, C. S. Ellis, A. R. Lebeck, IEEE Pervasive Computing, January-March 2005.
Self-Assembled Architectures and the Temporal Aspects of Computing, Chris Dwyer, Alvin R. Lebeck, and Daniel J. Sorin, in IEEE Computer, 38 (1), pages 56-64, January 2005.
Design Tools for Self-assembling Nanoscale Technology, C. Dwyer, V. Johri, J. P. Patwardhan, A. R. Lebeck, and D. J. Sorin, Institute of Physics Nanotechnology, volume 15, 2004.
Semi-empirical SPICE Models for Carbon Nanotube FET Logic, Chris Dwyer, Moky Cheung, and Daniel J. Sorin, In Proceedings of the Fourth IEEE Conference on Nanotechnology (IEEE-Nano), August 2004.
Tolerating Hard Faults in Microprocessor Array Structures, Fred A. Bower, Paul G. Shealy, Sule Ozev, and Daniel J. Sorin, In Proceedings of the International Conference on Dependable Systems and Networks (DSN), June 2004.
Circuit and System Architecture for DNA-Guided Self-Assembly of Nanoelectronics, Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck, Daniel J. Sorin, In Proceedings of the Foundations of Nanoscience: Self-Assembled Architectures and Devices (FNANO), April 2004.
Using Speculation to Simplify Multiprocessor Design, Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, and David A. Wood. In Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS), April 2004.
Exploiting Global Knowledge to Achieve Self-Tuned congestion Control for k-ary n-cube Networks, M. Thottethodi, A. R. Lebeck, S. Mukherjee, in IEEE Transactions on Parallel and Distributed Systems (IEEE TPDS), 15(3), pages 257-272, March 2004.
Communication Breakdown: Analyzing CPU Usage in Commercial Web Workloads, Jaidev P. Patwardhan, Alvin R. Lebeck, and Daniel J. Sorin. In Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2004.
The Synergy between Power-aware Memory Systems and Processor Voltage Scaling, X. Fan, C S. Ellis, A. R. Lebeck, in Power Aware Computer Systems (PACS'03), Springer-Verlag, December 2003.
Dynamic Verification of End-to-End Multiprocessor Invariants, Daniel J. Sorin, Mark D. Hill, and David A. Wood. In Proceedings of the International Conference on Dependable Systems and Networks (DSN-3), June 2003.
Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared Memory Multiprocessors, Milo M. K. Martin, Pacia J. Harper, Daniel J. Sorin, Mark D. Hill, and David A. Wood. In Proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA), June 2003.
Quantifying Instruction Criticality for Shared Memory Multiprocessors, Tong Li, Alvin R. Lebeck, and Daniel J. Sorin. In Proceedings of the 15th Symposium on Parallelism in Algorithms and Architectures (SPAA), June 2003.
Currentcy: Unifying Policies for Resource Management, H. Zeng, C. Ellis, A. Lebeck, A. Vahdat, May 2002, in USENIX 2003, June 2003.
BLAM: A High-Performance Routing Algorithm for Virtual Cut-Through Networks, M. S. Thottethodi, A. R. Lebeck, S. Mukherjee, in Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS), April 2003.
Simulating a $2M Commercial Server on a $2K PC, Alaa R. Alameldeen, Milo M. K. Martin, Carl J. Mauer, Kevin E. Moore, Min Xu, Daniel J. Sorin, Mark D. Hill, and David A. Wood. IEEE Computer, volume 36, number 2, February 2003.
Analytic Evaluation of Shared-Memory Architectures, Daniel J. Sorin, Jonathan L. Lemon, Derek L. Eager, and Mary K. Vernon. Transactions on Parallel and Distributed Systems (TPDS), volume 14, number 2, February 2003.
ECOSystem: Managing Energy as a First Class Operating System Resource, H. Zeng, X. Fan, C. Ellis, A. R. Lebeck, and A. Vahdat, in Proceedings of the Tenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS X), October 2002.
A Large, Fast
Instruction Window for Tolerating Cache Misses, A. R. Lebeck, J.
Koppanalil, T. Li, J. Patwardhan, E. Rotenberg, in Proceedings of the
29th International Symposium on Computer Architecture (ISCA), May 2002.
A Programmable
Memory Hierarchy for Prefetching Linked Data Structures, C. Yang, A. R.
Lebeck, in Proceedings of the 4th International Symposium on High Performance
Computing (ISHPC-IV), Springer-Verlag, May 2002, Japan.
Modeling of DRAM
Power Control Policies Using Deterministic and Stochastic Petri Nets, X.
Fan, C. S. Ellis, A. R. Lebeck, in Proceedings of the Workshop on
Power-Aware Computer Systems (PACS'02), Springer-Verlag, February,2002.
Recursive Array
Layouts and Fast Parallel Matrix Multiplication, S. Chatterjee, A. R.
Lebeck, Praveen K. Patnala, M. Thottethodi, in IEEE Transactions on Parallel
and Distributed Systems (IEEE TPDS), 2002.
Memory Controller
Policies for DRAM Power Management, X. Fan, C. S. Ellis, A. R. Lebeck, in
Proceedings of the International Symposium on Low Power Electronics and Design
(ISLPED) August, 2001.
Locality vs. Criticality, S. Srinivasan, R. Ju, A. R. Lebeck, C. Wilkerson, in Proceedings of the International Symposium on Computer Architecture (ISCA), June 2001.
Exact Analysis of the Cache Behavior of Nested Loops, S. Chatterjee, E. Parker, P. Hanlon, A. R. Lebeck, in Proceedings of the International Symposium on Programming Language Design and Implementation (PLDI), June 2001.
Self-Tuned Congestion Control for Multiprocessor Networks, M. S. Thottethodi, A. R. Lebeck, S. Mukherjee, in Proceedings of the Seventh International Symposium on High Performance Computer Architecture (HPCA-7), January 2001
The Combinatorics of Cache Misses During Matrix Multiplication, P. J. Hanlon, D. Chung, S. Chatterjee, D. Genius, A. R. Lebeck, and E. Parker, in the Journal of Computer Sciences and Systems, 2000.
Power Aware Page Allocation, Alvin R. Lebeck, Xiaobo Fan, Heng Zeng, Carla S. Ellis, in Proceedings of the Ninth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS IX), November 2000.
Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions, C. Yang, B. Sano, and A. R. Lebeck, In IEEE Transactions on Computers, 49(9), September 2000.
Every Joule is Precious: The Case for Revisiting Operating System Design for Energy Efficiency, A. Vahdat, A. R. Lebeck, C. S. Ellis, 9th ACM SIGOPS European Workshop, September 2000.
Push vs. Pull: Data Movement for Linked Data Structures, Chia-Lin Yang and Alvin R. Lebeck, International Conference on Supercomputing 2000 (ICS '00), May 2000.
Load Latency Tolerance In Dynamically Scheduled Processors, Srikanth T. Srinivasan and Alvin R. Lebeck, in the Journal of Instruction-Level Parallelism (JILP), Volume 1, October 1999 ( http://www.jilp.org/vol1) (Invited Paper)
Network I/O with Trapeze, Jeff Chase, Darrell Anderson, Andrew Gallatin, Alvin Lebeck, and Ken Yocum, 1999 Hot Interconnects Symposium, August 1999.
Annotated Memory References: A Mechanism for Informed Cache Management, A. R. Lebeck, D. R. Raymond, C. Yang, M. S. Thottethodi, Euro-Par '99, (Research Note) August 1999.
Recursive Array Layouts and Fast Matrix Multiplication, S. Chatterjee, A. R. Lebeck, P. K. Patnala, M. S. Thottethodi, in Proceedings of the 11th ACM Symposium on Parallel Algorithms and Architectures (SPAA '99), June 1999.
Nonlinear Array Layouts for Hierarchical Memory Systems , S. Chatterjee, V. Jain, A. R. Lebeck, S. Mundhra, M. Thottethodi, in Proceedings of the 13th ACM International Conference on Supercomputing (ICS '99) June 1999.
Cache Conscious Programming in Undergraduate Computer Science Alvin R. Lebeck, in Proceedings of the ACM SIGCSE Technical Symposium on Computer Science Education (SIGCSE '99), March 1999.
Load Latency Tolerance In Dynamically Scheduled Processors Srikanth T. Srinivasan and Alvin R. Lebeck, ACM/IEEE International Symposium on Microarchitecture (MICRO), November 1998. Best paper award
Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications Chia-Lin Yang, Barton Sano, and Alvin R. Lebeck, ACM/IEEE International Symposium on Microarchitecture (MICRO), November 1998
Tuning Strassen's Matrix Multiplication for Memory Efficiency Mithuna S. Thottethodi, Siddhartha Chatterjee, and Alvin R. Lebeck in Proceedings of Supercomputing '98, November 1998 postscript (nominated for best student paper)
WCDRAM: Fully Associative Integrated Cached DRAM with Wide Cache Lines Ram Prasad Koganti and Gershon Kedem, In 11th Annual International Symposium on High Performance Computing Systems (HPCS'97), July 1997
Architecture-Efficient Strassen's Matrix Multiplication: A Case Study of Divide-and-Conquer Algorithms V. P. Pauca, X. Sun, S. Chatterjee, and A. R. Lebeck, In International Linear Algebra Society (ILAS) Symposium on Algorithms for Control, Signals, and Image Processing, June 1997.
Cut-Through Delivery in Trapeze: An Exercise in Low-Latency Messaging Ken Yocum, Jeff Chase, Andrew Gallain, and Alvin R. Lebeck, in Proceedings of IEEE International Symposium on High Performance Distributed Computing (HPDC), August 1997 (postscript)
Active Memory: A New Abstraction For Memory System Simulation Alvin R. Lebeck and David A. Wood, ACM Transactions on Modeling and Computer Simulation. 7(1), pages 42-77, January 1997 This is an extended version of the paper that appeared in SIGMETRICS '95
Distributed Prefetch-buffer/Cache Design for High Performance Memory System. Thomas Alexander and Gershon Kedem, Procedings HPCA-2. pp. 254-263, Feb. 1996.